Faces Calculator3 I2C Control Protocol

1. Hardware Interface

1.1 IRQ Behavior

After a key is released and a valid key code is generated, the module pulls IRQ low. After the host directly reads the 1-byte key data, the module returns IRQ high.

Key released; data generated          Host reads key data
              |                                |
--------------+ IRQ low (0) ------------------+ IRQ high (1)

2. Communication Overview

The module supports three types of I2C operations:

All multi-byte data is transmitted from left to right as shown in the tables.

3. Key-Data Read

When IRQ is low, the host directly reads exactly 1 byte from the module without first writing a register address. Key data is generated when the key is released.

3.1 Key Matrix and Returned Values

The module uses a 5-row x 4-column key matrix. A normal short press returns the single-byte ASCII code of the corresponding character.

3.2 Long-Press Special Codes

Only A and = define special long-press behavior. When either key is held for more than 400 ms and then released, the following control code is returned:

Holding any other key returns its normal ASCII code.

3.3 Event Buffering

The module retains only one unread key byte and does not provide a key FIFO. If new key data is generated before the host reads the previous data, the previous byte may be overwritten. The host should read promptly after detecting that IRQ is low.

4. Register Address Map

5. Register Reads

5.1 Read Procedure

1. The host writes a 1-byte register address to the module.
2. The host issues a repeated START or a new I2C read transaction.
3. The module returns data from the selected register block.

The host must not read more than the maximum length specified below.

5.2 Readable Register Blocks

Device Type ID

MCU UID

The UID is read into a cache at power-on. To read the complete UID, start at 0xE0 and read 12 bytes. The byte order follows ascending STM32 UID storage addresses.

Firmware Version and I2C Address

Firmware v03 returns 0x03 as firmware_version. i2c_address is the current 7-bit slave address and does not include the read/write direction bit.

6. Command Writes

The public command write format is exactly 2 bytes:

[register address] [data]

6.1 System Reset / IAP Entry (0xFD)

Example:

[0xFD] [0x01]

6.2 Change I2C Address (0xFF)

The I2C specification reserves 0x00-0x07 and 0x78-0x7F. These addresses are not recommended even where the firmware accepts them.

Example: change the module address to 0x20:

[0xFF] [0x20]

After the write completes, the host must use the new address for further communication. Wait for the configuration write to complete and read 0xFF at the new address to confirm the change. A written value of 0x00 or greater than 0x7F is ignored.

7. Host Access Examples

All addresses in the following pseudocode are 7-bit I2C addresses.

7.1 Read Key Data

uint8_t key_code;
i2c_read(device_address, &key_code, 1);

7.2 Read Firmware Version and Current Address

uint8_t reg = 0xFE;
uint8_t info[2];
i2c_write(device_address, &reg, 1);
i2c_read(device_address, info, 2);

7.3 Read the Complete UID

uint8_t reg = 0xE0;
uint8_t uid[12];
i2c_write(device_address, &reg, 1);
i2c_read(device_address, uid, 12);

8. Usage Notes

• The host should prioritize reading the 1-byte key data after detecting that IRQ is low.
• A key code is generated when the key is released; holding a key does not generate repeat events.
• The module returns one key code at a time. It does not provide the complete matrix state or a multi-key combination state.
• Register reads and key-data reads use different transaction flows and must not be mixed.
• After changing the I2C address, retain or rediscover the new address so the device remains reachable after subsequent startups.